(1) Field of the Invention
The present invention relates to a data signal loading circuit for performing high-speed signal transmission and high-speed data signal loading, a display panel driving circuit and an image display apparatus equipped with the data signal loading circuit, and particularly to technology that is useful for a driver which drives a liquid crystal panel.
(2) Description of the Related Art
As shown in FIG. 7, a conventional data signal loading circuit 100 includes: a latch circuit L1 (i) in which small-amplitude differential clock signals CKP and CKN are inputted to a non-inverting input terminal and an inverting input terminal of a comparator CMP1, respectively, and small-amplitude differential data signals DAP and DAN are inputted to a non-inverting input terminal and an inverting input terminal of a comparator CMP2, respectively, and (ii) which loads a data signal DL1 outputted from the comparator CMP2, at the rise of a clock signal CL1 outputted from the comparator CMP1; and a latch circuit L2 which loads the data signal DL1 at the rise of a clock signal CL2 outputted from an inverter circuit INV1 which generates a reverse-phase signal of the clock signal CL1 outputted from the comparator CMP1.
The configuration in FIG. 7 enables the data signal DL1 to be loaded synchronously with the rise of the small-amplitude differential clock signals CKP and CKN.
As shown in FIG. 9, a conventional data signal loading circuit 200 includes: a latch circuit L1 (i) in which small-amplitude differential clock signals CKP and CKN are inputted to a non-inverting input terminal and an inverting input terminal of a comparator CMP1, respectively, and the small-amplitude differential clock signals CKP and CKN are inputted to an inverting input terminal and a non-inverting input terminal of a comparator CMP2, respectively, and small-amplitude differential data signals DAP and DAN are connected to a non-inverting input terminal and an inverting input terminal of a comparator CMP3, respectively, and (ii) which loads a data signal DL1 outputted from the comparator CMP3, at the rise of a clock signal CL1 outputted from the comparator CMP1; and a latch circuit L2 which loads a data signal DL1 at the rise of a clock signal CL2 outputted from the comparator CMP2.
It should be noted that Japanese Patent No. 3833064 (Patent Reference 1), for example, is known as prior art document information of the invention in the present application.
According to the configuration of the conventional data signal loading circuit 100, the characteristics of the comparators CMP1 and CMP2 for amplifying the small-amplitude differential signals vary according to conditions such as frequency, power supply voltage, process, temperature. Thus, when the duty ratio between the clock signal CL1 and the data signal DL1 deviates significantly, there is a possibility that the latch circuit L1 and the latch circuit L2 will be unable to load the data signal DL1, and there is a possibility of causing misoperation particularly when the data signal loading circuit operates at high speed, and so on.
Hereinafter, the behavior of each signal in the conventional data signal loading circuit 100 shown in FIG. 7 shall be described using the timing chart in FIG. 8.
First, the rise and fall of the clock signal CL1 are outputted delayed from the rise and fall of the small-amplitude differential clock signal CKP inputted to the comparator CMP1, by a delay time T1 and a delay time T2, respectively. At this time, with the variation of the characteristics of the comparator CMP1 in response to conditions such as frequency, power supply voltage, process, and temperature, the delay time T1 and the delay time T2 do not become equal and the duty ratio between the high interval and the low interval of the clock signal CL1 deviates. Furthermore, the rise and fall of the clock signal CL2 are outputted delayed from the rise and fall of the clock signal CL1 inputted to the inverter INV1, by a delay time T3 and a delay time T4, respectively.
In the case of such a circuit configuration, it is predicted that a total delay time TS1 for the rise of the clock signal CL1 inputted to the latch circuit L1 becomes TS1=T1, and a total delay time TS2 for the rise of the clock signal CL2 inputted to the latch circuit L2 becomes TS2=T2+T3, and the total delay time TS1 and the total delay time TS2 will be significantly different.
In this manner, in the conventional data signal loading circuit 100, when the timing for both the rise and fall of the output signal of the comparator CMP1 is used in data signal loading, and the like, in an internal circuit of the data signal loading circuit 100, the inability to perform correct data signal loading arises, and it is assumed that this becomes more prominent as the operating speed of the data signal loading circuit 100 becomes higher.
In the structure of the conventional data signal loading circuit 200, the characteristics of the comparators CMP1, CMP2, and CMP3 for amplifying the small-amplitude differential signals vary according to conditions such as frequency, power supply voltage, process, temperature, in the same manner as in the data signal loading circuit 100. However, since the delay times for the rise of the clock signal CL1 and the clock signal CL2 outputted from the comparator CMP1 and the comparator CMP2, respectively, are approximately equal, it becomes easy to load the data signal DL1 synchronously with the rise of the small-amplitude clock signals CKP and CKN, compared to the data signal loading circuit 100.
Hereinafter, the behavior of each signal in the conventional data signal loading circuit 200 shown in FIG. 9 shall be described using the timing chart in FIG. 10.
First, the rise and fall of the clock signal CL1 are outputted delayed from the rise and fall of the small-amplitude differential clock signal CKP inputted to the comparator CMP1, by a delay time T1 and a delay time T2, respectively. The rise and fall of the clock signal CL2 are outputted delayed from the rise and fall of the small-amplitude differential clock signal CKN inputted to the comparator CMP2, by a delay time T3 and a delay time T4, respectively. At this time, when the comparator CMP1 and the comparator CMP2 have the same circuit configuration, the delay time T1 and delay time T3, and the delay time T2 and delay time T4 become approximately equal delay times. In addition, when the comparator CMP1 and the comparator CMP2 have the same circuit configuration according to conditions such as frequency, power supply voltage, process, and temperature, the duty ratio between the high interval and the low interval deviate in the same manner.
In the case of such a circuit configuration, a total delay time TS1 for the rise of the clock signal CL1 inputted to the latch circuit L1 becomes TS1=T1, and a total delay time TS2 for the rise of the clock signal CL2 inputted to the latch circuit L2 becomes TS2=T3, and the total delay time TS1 and the total delay time TS2 become approximately equal.
Next, FIG. 11 shows a circuit configuration diagram of the comparators CMP1, CMP2, and CMP3 which configured of transistors.
FIG. 11 shows a configuration in which the comparators are connected in multiple-stages.
The conventional comparators shown in FIG. 11 include, for example, a comparator C1, a comparator CS, and an inverter I1. The comparator C1 includes: a constant current source transistor MP1; transistors MP2 and MP3 to which the drain of MP1 is connected and a differential signal is inputted; and transistors MN1 and MN2 to which the drains of MP2 and MP3 are respectively connected. The comparator CS includes: transistors MN3 and MN4 to which the drains of MP2 and MP3 are respectively connected; a transistor MP4 having a gate and drain to which the drain of MN3 is connected; and a transistor MP5 having a gate to which the drain of MN3 is connected. The comparator CS outputs the drains of MP5 and MN4 to the inverter I1. The inverter I1 includes transistors MP6 and MN5 having gates to which the output signal of the comparator CS is inputted. The inverter I1 outputs the drains of MP6 and MN5, and has a function for shaping the output signal of the comparator CS.
When the comparators shown in FIG. 11 are applied to the comparators CMP1 to CMP3 of the conventional data signal loading circuit 200, there is concern over an increase in consumption current in the comparator CMP1 and the comparator CMP2 since these comparators are connected in multiple-stages. In addition, as shown in FIG. 12, when a configuration which connects the comparator C1 in two stages is assumed, as a comparator C2, in place of the comparator C1 shown in FIG. 11, consumption current increases further as the number of stages of the comparators increases. Furthermore, the load connected to the small-amplitude differential clock signals CKP and CKN are the comparator CMP1 and the comparator CMP2, and the load connected to the small-amplitude differential data signals DAP and DAN is only the comparator CMP3. As such, the small-amplitude differential data signals DAP and DAN become approximately half compared with the small-amplitude differential clock signals CKP and CKN, and there is the problem that the same impedance matching is not possible between the clock signals and the data signals.